Intel's EMIB-T packaging is gaining traction with Google's forthcoming TPU as TSMC's CoWoS capacity strains under surging AI demand.
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Intel EMIB-T challenges TSMC CoWoS as 2 suppliers enter Google TPU orbit
Intel's EMIB-T packaging is gaining traction with Google's forthcoming TPU as TSMC's CoWoS capacity strains under surging AI demand.
Intel's Embedded Multi-die Interconnect Bridge technology is pulling two more Taiwanese suppliers into Google's tensor processing unit supply chain, as TSMC's Chip-on-Wafer-on-Substrate capacity fails to keep pace with AI chip demand growing at a 64% compound annual rate between 2025 and 2027, according to The Information Network.
"The area customers most want improvement in is energy efficiency," Kevin Zhang, senior vice president of business development at TSMC, said at a conference in Amsterdam on May 28. "This is true across the board, whether you are the edge guy, smartphone, mobile, IoT application, or high-performance AI data center."
Taiwan's Powerchip Semiconductor and AP Memory Technology Corp have entered Google's TPU supply chain evaluation, according to supply chain reports from Taiwan. AP Memory's silicon capacitors are playing a key role in MediaTek's design of the Google AI chips, with SiCap production expected to reach 10,000 capacitors by the end of 2027. Intel's EMIB-T technology, which uses through-silicon vias for connectivity, offers a lower-cost alternative to CoWoS — packages for Nvidia's Rubin-class processors can approach $1,000 each due to the large silicon interposer, according to industry packaging economics cited by The Information Network.
The outcome hinges on Intel's production yields, which must improve from about 90% to 98% for the economics to work at scale, analysts have warned. Google is also weighing whether to send chip designs directly to TSMC rather than working through MediaTek, a move that would cut costs but bypass the Intel-Google-MediaTek partnership that brought EMIB-T into consideration.
CoWoS Capacity Constraints Create an Opening
TSMC's CoWoS capacity is effectively pre-allocated to a small number of customers. Nvidia alone accounts for roughly 60% of total demand, according to The Information Network. Broadcom and AMD absorb another 26%, leaving limited availability for second-tier AI chip developers and custom ASIC vendors. TSMC is targeting CoWoS capacity of 130,000 to 160,000 wafers per month by 2026 to 2027, but demand continues to outpace supply as hyperscalers deploy custom inference accelerators alongside traditional AI training GPUs.
Intel has marketed EMIB as a cost-effective alternative. Unlike CoWoS, which uses a full silicon interposer connecting logic and high-bandwidth memory across the entire package, EMIB embeds localized silicon bridges within the substrate, reducing silicon area and lowering cost. Intel claims EMIB supported approximately 6 times reticle size in 2024 and is targeting 8 times in 2026 and as much as 12 times by 2028. The company already operates advanced packaging facilities in New Mexico and Malaysia and is expanding capacity in Arizona alongside its Fab 52 and Fab 62 buildout.
What's at Stake for Investors
For Intel, winning Google's TPU business would represent more than a packaging revenue stream — it would be a strategic entry into custom AI silicon at a time when the company is repositioning its foundry services. Meta is also evaluating EMIB-T for its MTIA accelerators, according to industry reports, suggesting the technology could gain multiple hyperscaler customers if yields prove competitive.
TSMC shares have gained about 40% year to date in 2026, reflecting strong conviction in its AI positioning. The company's first-quarter 2026 revenue rose 40.6% year over year to $35.9 billion, with gross margin at 66.2%. But the packaging bottleneck represents a structural risk: if Intel can demonstrate competitive yields at scale, it could capture a meaningful portion of incremental AI packaging demand in a market where supply — not technology — remains the binding constraint. Intel does not need to displace CoWoS to benefit; it only needs to capture a portion of the incremental demand in a supply-constrained market.
This article is for informational purposes only and does not constitute investment advice.
[1] AI Chip Packaging War Escalates! TSMC CoWoS Capacity Under Pressure, Intel EMIB-T Fills in for Google TPU Supply Chain[2] TSMC races to expand AI chip capacity while CPO and CoWoS move to center stage[3] Intel’s EMIB-T Packaging Pulls Two More Taiwanese Suppliers Into Google’s TPU Orbit as TSMC’s CoWoS Strains - Wccftech[4] TSMC executive drops blunt message on AI chip’s next frontier - thestreet.com[5] AI Chip Packaging Constraints Create an Opening for Intel’s EMIB Technology - AOL.com
