TSMC develops EMIB-like packaging tech, stock surges 7.6%

TSMC is building an advanced chip-packaging technology that mirrors Intel's EMIB, escalating the battle between the two foundry giants for dominance in the $44 billion AI chip packaging market.

Taiwan Semiconductor Manufacturing Co. is developing a chip-packaging technique internally referred to as "EMIB-like," according to two people familiar with the project, as the world's largest contract chipmaker seeks to challenge Intel Corp.'s embedded multi-die interconnect bridge technology. TSMC's American depositary receipts surged 7.6% on July 30 after the news, the biggest single-day gain in three months.

"TSMC's move into EMIB-like packaging signals they recognize CoWoS alone won't meet the industry's long-term demand for heterogeneous integration," said Samuel Wang, semiconductor analyst at Arete Research. "The question is whether they can match Intel's 98% yield on EMIB-T before customers commit to long-term supply agreements."

Intel's EMIB technology, which uses embedded micro-silicon bridges to connect chiplets instead of a full silicon interposer layer, has reached a 98% yield rate on its EMIB-T variant and secured orders from Nvidia Corp., Google LLC and OpenAI. The approach reduces manufacturing cost and complexity by placing bridges only where connections are needed, similar to building small footbridges between two land masses rather than paving an entire road.

TSMC has long dominated AI chip packaging through its CoWoS (chip-on-wafer-on-substrate) technology, which underpins Nvidia's H100 and Blackwell-series graphics processors. But even as the company aggressively expands CoWoS capacity, Nomura estimates supply constraints will persist through at least 2027, with TSMC targeting 2 million CoWoS wafers annually by that year — of which Nvidia would consume roughly 55%.

Why EMIB Matters Now

The packaging arms race is intensifying as AI chip designs grow too large for a single silicon die. Advanced packaging — the final stage of semiconductor production where separate pieces of silicon are assembled into a single unit — has become a bottleneck for AI compute capacity. TSMC's CoWoS capacity is sold out through 2026, and the company has pursued multiple parallel paths to expand: a glass-substrate CoWoS development program and a CoPoS (chip-on-panel-on-substrate) pilot line in Tainan, southern Taiwan, targeting mass production in the second half of 2028. Nvidia's next-generation Feynman architecture GPU is expected to be the first product to use CoPoS packaging.

Intel, meanwhile, is rebuilding its foundry business after years of manufacturing setbacks. Its 18A process technology is expected to reach high-volume production in 2026, and the company has landed marquee foundry customers including Apple Inc. and Tesla Inc. EMIB serves as a key differentiator for Intel's foundry offering, allowing it to pitch customers on a combined process-and-packaging solution that TSMC cannot yet fully match.

Samsung Electronics Co. is also accelerating its own glass-substrate packaging roadmap, making the segment a three-way contest among the world's largest semiconductor manufacturers.

Investment Implications

For investors, the packaging battle introduces a new variable into the foundry competitive landscape. TSMC's stock trades at roughly 22 times forward earnings, a premium to Intel's 18 times, reflecting its dominant position in leading-edge logic manufacturing. But if Intel's EMIB technology captures meaningful share in the AI packaging segment — particularly with marquee customers like Nvidia — it could narrow the valuation gap over time.

Nvidia, which relies on TSMC for both wafer fabrication and CoWoS packaging, stands to benefit from any packaging capacity expansion regardless of which technology wins. The company's decision to also evaluate Intel's EMIB for a future multi-die processor, as previously reported, gives it leverage in pricing negotiations with both suppliers.

TSMC's EMIB-like project is still in early development, and the company has not disclosed a timeline for commercial introduction. The project adds to a packaging technology portfolio that already includes CoWoS, InFO (integrated fan-out), and SoIC (system-on-integrated-chips), giving TSMC the broadest packaging toolkit in the industry — provided it can match Intel's yield and cost metrics.

This article is for informational purposes only and does not constitute investment advice.