SK Hynix hires US engineers for 3D stacked DRAM to power edge AI

SK Hynix Inc. is recruiting design engineers in San Jose for 3D stacked DRAM-on-Logic, a packaging technology that stacks memory directly atop logic chips to overcome bandwidth constraints limiting on-device AI in smartphones.

"Memory and logic integration is the breakthrough needed to maximize AI performance within existing architecture limits," SK Hynix's development head said at the TSMC Technology Symposium in April, outlining the technology as one of three strategic pillars alongside custom HBM and high-bandwidth flash.

The approach replaces traditional Package-on-Package packaging, which stacks two chips vertically, with a 3D architecture that shortens interconnect distance and increases data-transfer channels within the same footprint. Apple's A19 Pro, the current flagship smartphone processor, tops out at 75.8GB/s of memory bandwidth — a figure that analysts say is insufficient for real-time AI inference on device.

SK Hynix, which dominates the HBM market with roughly two-thirds of Nvidia's HBM4 supply for the Vera Rubin platform, is extending its memory leadership into edge computing. The move positions the company to capture demand from Apple and Qualcomm as smartphone makers race to deliver AI features that run locally rather than in the cloud.

Why Memory Bandwidth Became the Bottleneck

Smartphone chipsets from Apple, Qualcomm, MediaTek and Samsung have made significant gains in AI compute capability, but memory bandwidth has not kept pace. The traditional PoP packaging used in mobile application processors limits the number of data channels between DRAM and the logic chip, creating a bottleneck for large language models that require rapid data movement.

SK Hynix's 3D stacked DRAM-on-Logic addresses this by placing memory directly on top of the processor, connected through thousands of vertical interconnects rather than the limited edge connections in PoP. The result is higher bandwidth at lower power — a combination essential for battery-powered devices running AI workloads.

The company has formed a partnership with an unnamed US customer to commercialize the technology. Industry analysts point to Apple as the likely partner, given the iPhone maker's reported shift from InFO-PoP to Wafer-Level Multi-Chip Module packaging for its upcoming A20 Pro chip.

Rivals Race to Solve the Memory Problem

SK Hynix is not alone in pursuing this opportunity. Qualcomm is developing 3D DRAM for its Neural Processing Units in partnership with Chinese memory maker CXMT. Samsung is working on Low Latency Wide DRAM that mimics HBM's design for mobile devices, targeting 150 percent higher bandwidth than LPDDR5X. Huawei is also exploring HBM-style memory for smartphones, though the technology's high cost and low yields remain obstacles.

The HBM market is projected to reach $54.6 billion in 2026, according to Bank of America, and SK Hynix's expansion into edge AI memory represents a natural extension of its dominance in that space. The company's Yongin Y1 factory began equipment procurement in July, while its Cheongju NAND line is slated for roughly 100 trillion won in expansion investment. HBM4E 12-layer samples have already been delivered to key customers.

For investors, the question is timing. Apple's iPhone 18 Pro has reportedly entered mass production, making it unlikely that 3D stacked DRAM will appear in the A20 Pro. A debut in 2027 or later is more probable. SK Hynix shares, listed on the Korea Exchange and recently debuting in the US market via a $26.5 billion listing, give investors direct exposure to a company building its business at the center of both cloud and edge AI memory supply.

This article is for informational purposes only and does not constitute investment advice.